Field of the Invention
This invention relates generally to the field of computer processors and software. More particularly, the invention relates to an apparatus and method for page level monitoring.
Description of the Related Art
In current binary translation implementations, the binary translation software is loaded from persistent storage such as the platform flash read only memory (ROM) into a predefined area in the system random access memory (RAM). The dynamically translated binary code is then stored in a part of the remaining system RAM, called the “Translation Cache.” The rest of the remaining memory is available for native software (e.g., x86) including the basic input output system (BIOS), operating system (OS) and applications.
Current hardware/software co-designed binary translation platforms enable dynamic binary optimizations through hidden binary translation (BT) software. Such software delivers increased performance in a power efficient fashion and also enables new instruction set architecture (ISA) extensions transparent to the OS and applications. One of the challenges of current binary translation systems is the detection of translation consistency violations occurring due to the following causes:
(1) the virtual page, where the original instruction stream resides, has been remapped to a different physical page which has different instruction stream contents;
(2) the original instruction stream has been modified by the current processor (e.g., via Self-Modifying Code) or remote processors (e.g., via Cross Modifying Code); and
(3) direct memory access (DMA) devices modify the original instruction streams.
Addressing the above issues often results in investing a very complex, dedicated, and expensive processor as well as new ISA extensions. While it is possible for new processor architectures to take such an aggressive step, it may be difficult or impractical for existing matured micro-architectures to do the same.